HKSTP announces the launch of the Student Internship Programme (SIP) 2026, which has been open for applications since mid-May 2026.-SIP 2026 is designed to equip students with essential skillsets, industry exposure, and professional networks, supporting their transition into the innovation and technology (I&amp;T) sector upon graduation. The programme also enables companies to engage early with emerging talent and contribute to workforce development.-Eligible HKSTP partner companies can receive funding support to employ qualified student interns, providing students with meaningful, hands-on experience in real-world business environments.-*Please note that funding support is allocated on a&nbsp;first-come, first-served basis.-For further details, please feel free to contact TecONE at 2629 2383 or sip@hkstp.org.

HKSTP Student Internship Programme 2026

Blooming with AI: HKSTP Summer Talent Fest 2026

HKSTP Global Internship 2026

HYAB Youth Start-up Internship Programme (YSIP).

“AI for All” Inclusive Programme - Talent Foundry

-Conduct Hands-On Cloud Research &amp; Experimentation: Design, prototype, and evaluate advanced cloud-native architectures, distributed systems, and emerging cloud technologies through rigorous technical experimentation and proof-of-concept (PoC) implementations.-Drive Technical Feasibility &amp; R&amp;D Initiatives: Lead deep-dive feasibility studies and technical benchmarking for complex cloud initiatives, directly contributing code, architectures, and experimental models across all research stages.-Pioneer Technical Innovation: Investigate cutting-edge cloud paradigms (such as serverless computing, edge-cloud integration, multi-cloud optimization, or container orchestration) and translate theoretical concepts into practical, scalable R&amp;D solutions.-Collaborate &amp; Guide Technical Execution: Work closely with cross-functional teams to integrate research outcomes into practical project pipelines while providing technical guidance and mentoring team members on best practices.

Project Engineer

<ul><li>Design and develop end-to-end systems across mobile applications (iOS &amp; Android), backend services, APIs, and data layers</li><li>Take ownership of system architecture, including component boundaries, data flow, and client–server responsibilities</li><li>Collaborate with cross-functional teams to translate real-world operational and research requirements into scalable technical solutions</li><li>Build and maintain backend services and integrations supporting LocoBikeʼs core mobility and operations platforms</li><li>Work closely with mobile apps, understanding performance, latency, reliability, and real-world usage constraints</li><li>Use Python to support R&amp;D activities, including: </li></ul><ol><li>Data processing and analysis </li><li>Algorithm prototyping and experimentation </li><li>Supporting research validation and technical documentation </li></ol><ul><li>Leverage AI coding agents to accelerate development while: </li></ul><ol><li>Clearly defining problems and constraints </li><li>Critically reviewing and validating generated code </li><li>Ensuring correctness, performance, and maintainability </li></ol><ul><li>Review AI-assisted outputs with a strong verification mindset, considering edge cases, failure modes, and long-term implications</li><li>Continuously improve system design, code quality, and development workflows Education &amp; Experience Bachelorʼs degree or above in Computer Science, Engineering, Data Science, or a related discipline; Masterʼs degree or PhD preferred.</li></ul>

R&D Engineer

Job Responsibilities<ol><li> Responsible for the top-level architecture planning, technical route formulation and scheme selection of humanoid robots, and oversee the design and iterative optimization of full-stack mechanical, hardware, software and communication architectures.</li><li> Lead the integrated design of multi-dimensional robot modules, and solve core architectural problems such as cross-domain coupling, adaptation and collaborative operation of machinery, hardware, communication and software systems.</li><li> Conduct top-level reliability design for humanoid robot complete machines, establish a comprehensive reliability system, and optimize equipment durability, anti-interference ability and complex environmental adaptability.</li><li> Focus on producible architecture design, continuously optimize production, assembly and testing processes, eliminate mass production risks in advance, and support stable large-scale product delivery.</li><li> Formulate unified complete-machine architecture design standards and technical specifications, coordinate cross-team technical implementation, and tackle systematic technical challenges in R&amp;D and mass production stages.</li></ol>Job Requirements<ol><li> Master’s degree or above in Robotics, Automation, Mechatronics, Computer Science or related fields, with over 10 years of practical experience in intelligent robot complete machine architecture design.</li><li> Proficient in the full-stack architecture of humanoid robots including mechanical structure, hardware circuit, bus communication and system software, with comprehensive capabilities of full-domain system design and integration.</li><li> Solid experience in mass-production-oriented architecture design, familiar with robot manufacturing processes, capable of controlling product yield and production cost through top-level architectural optimization.</li><li> Master complete-machine reliability design and failure analysis methodologies, able to guarantee robot operational stability, durability and safety via systematic architectural optimization.</li><li> Familiar with mainstream robot development architectures and communication protocols, with outstanding systematic thinking, technical problem-solving capabilities and cross-departmental collaboration management skills.</li></ol>

系統架構師System Architect

Responsibilities 1. AI Agent development: build AI agents and tool calling with Mastra and the Vercel AI SDK. 2. AI generation: develop image, video and text generation features, orchestrating background jobs with Trigger.dev. 3. AI quality and cost: own model evaluation, tracing, and model selection across providers (OpenAI / Anthropic / Google). 4. Full‑stack development: ship frontend and backend features with Next.js, Supabase, shadcn/ui and TailwindCSS. 5. Engineering productivity: use AI coding tools such as Claude Code and Codex to keep raising development speed and quality.Requirements 1. Strong full‑stack fundamentals: expert in TypeScript, React and Next.js (App Router / Server Components / Server Actions); able to take a feature from design to production on your own. 2. Hands‑on LLM application experience: shipped a real project with at least one of Vercel AI SDK / Mastra / LangChain / OpenAI SDK; understand prompt design, tool calling, streaming and structured output. 3. Solid PostgreSQL schema design and SQL; experience with Supabase or a similar BaaS. 4. Heavy user of AI coding tools who reviews and verifies AI‑generated code and owns the final quality. 5. Fluent English reading; good communicator with strong ownership and self‑drive; writes clear technical docs.Nice to have 1. Experience with agent memory, RAG / vector search (pgvector, embeddings, rerank) or multi‑agent systems. 2. Built LLM evaluation (evals, LLM‑as‑judge) or production AI observability (traces, cost and latency analysis). 3. Worked on image / video generation products, or media processing with tools like ffmpeg. 4. Deployed on Vercel, Cloudflare Workers or Google Cloud; used Trigger.dev or a similar background job framework. 5. Built SaaS products (Clerk auth, Stripe subscription billing, i18n), or know hardware, manufacturing or supply chains.

AI Full-Stack Engineer (Next.js / AI Agent)

You will work on the core pipeline of the A2A Network multi-agent system — from agent registration and tool mounting to state machine orchestration — alongside a team whose backgrounds span fintech, data science, and complex systems engineering. This is a hands-on engineering internship: you will ship real components of a production system, not shadow work.Tech stack: Python · LLM / Prompt Engineering · LangChain / LangGraph / OpenClaw · State Machines · API IntegrationPositionAI Agent Engineer (Student Intern)LocationHong Kong Science Park (on-site)Duration3 consecutive months, full-time (not less than 40 hours per week)EligibilityFull-time students of local or non-local post-secondary / tertiary institutions, aged 18+, legally permitted to work in Hong KongSalaryCompetitive monthly salary, subsidised under HKSTP SIP (details at offer stage)

Fullstack Developer (Agentic Development)

Duties • Participate in a team to design and layout of high-speed ICs for optical fiber/wireline communications, Design, verification, simulation and optimization for amplifier, ADC/ DAC, bandgap, analog buffer, LDO, charge pump, voltage reference, PLL, oscillator, SerDes,etc. Create support documents. Requirements • Bachelor degree or above in Electronic Engineering. • Knowledge of analog and mixed-signal circuit design. • Familiar with simulation tools such as SPICE, SPECTRE • Experienced in high-speed circuit design is a plus good programming in Perl, TCL and Shellprogramming is preferred. • Applicant with less experience will be considered as Junior Analog Design Engineer • Knowledge in CMOS IC physical layout design and able to use various EDA tools. • Good understanding of semiconductor theory and structures of devices.

Junior/ Senior Analog Design Engineer

About the RoleWe are developing next-generation NPUs and computing systems with large-model inference as a primary application, and are looking for a senior architect with technical depth and a systems perspective to drive hardware architecture innovation, frontier technology exploration, and validation of key technical solutions.This role is centered on hardware architecture and requires combined hardware/software knowledge and analytical capability — understanding the execution characteristics of large models, compilers, and runtimes, and translating them into design and optimization decisions across chips, memory, interconnect, and complete systems. Strong emphasis is also placed on performance, energy efficiency, cost efficiency, and engineering feasibility under domestic process and supply-chain conditions.We welcome technical experts with deep expertise in at least one of the following areas — NPU chips, high-speed interconnect, or complete systems — and with a cross-domain perspective.Key Responsibilities<ol><li>Hardware architecture exploration for large-model inference. Research NPU compute architecture, memory hierarchy, data movement, and interconnect mechanisms around the requirements of large-model inference, and propose innovative ideas, architecture improvements, and alternative solutions with product value.</li><li>Workload analysis and hardware-software co-design. Analyze the compute, memory-access, and communication characteristics of representative models in stages such as Prefill and Decode; combined with operator mapping, compiler scheduling, runtime, and communication libraries, identify hardware bottlenecks and optimize resource allocation and hardware-software interfaces.</li><li>Focused research on key hardware technologies. Based on individual expertise, lead research and solution design in one or more of the following directions:</li></ol><ul><li>NPU and SoC architecture: compute units, memory hierarchy, NoC, memory controllers, host interfaces, and related IP.</li><li>Advanced packaging and memory: chiplet, 2.5D/3D packaging, stacked memory, and die-to-die interconnect.</li><li>Boards and multi-card interconnect: PCIe accelerator cards, OAM modules, inter-card interconnect, system topology, and communication mechanisms.</li><li>Systems and supernodes: multi-accelerator servers, rack-scale systems, and supernodes, balancing compute, interconnect, power, cooling, and mechanical constraints.</li></ul><ol><li>Domestic process adaptation and engineering feasibility. Evaluate constraints such as die area, frequency, power, yield, and interface capabilities against the maturity of domestic wafer fabrication, memory, packaging, substrate, and IP capabilities, and explore architecture implementation paths suited to the domestic supply chain.</li><li>Performance and cost-efficiency optimization. Under target model, precision, and service-latency requirements, evaluate effective throughput, energy efficiency, and multi-card scaling efficiency; factoring in manufacturing, packaging, testing, memory, board, and system costs, optimize inference capability per unit cost and total cost of ownership (TCO).</li><li>Modeling, validation, and results delivery. Quantitatively compare the benefits and risks of candidate solutions through performance modeling, simulation, prototype verification, and sample testing; collaborate with chip, packaging, hardware, and software teams to move research outcomes into product design. Qualifications· Bachelor's degree or above in Microelectronics, Computer Science, Electronic Engineering, Communications, or a related field, with extensive hardware R&amp;D experience and experience in architecture design, technology research, or complex system development.· Chip direction: NPU or high-performance computing chips, with solid knowledge of compute units, memory hierarchy, on-chip interconnect, SoC integration, and related IP.· Hardware-software co-design knowledge that underpins hardware architecture design — understanding how models and operators are mapped to hardware through compilers and runtimes, and the ability to work with software teams to analyze performance issues and translate them into hardware requirements and design trade-offs.· A cross-layer systems perspective, able to understand the dependencies among chips, packaging, boards, interconnect, and complete systems. Expert-level depth in every direction is not required.· Understanding of domestic semiconductor process and supply-chain conditions, able to incorporate manufacturing, IP, packaging, and production constraints into solution evaluation.Preferred Qualifications· Architecture design experience with NPU chips or computing systems for large-model inference.· A proven track record of improving hardware utilization, inference performance, or deployment cost through hardware-software co-design.· Experience developing PCIe/OAM boards, multi-GPU servers, liquid-cooled racks, or supernodes.· Experience in joint development with foundries, packaging houses, IP vendors, or system manufacturers.The OpportunityThis role explores hardware innovation for next-generation NPU and computing systems grounded in the real-world needs of large-model inference, combining frontier technology with domestic engineering conditions to deliver product solutions with performance advantages, cost competitiveness, and mass-production viability. Specific research directions can be tailored to the candidate’s expertise.</li><li>· Experience in hardware performance modeling, system simulation, FPGA prototyping, or cost modeling.</li><li>· Project experience with chiplet, advanced packaging, stacked memory, UCIe, or multi-card high-speed interconnect.</li><li>· Experience in chip design, tape-out, mass production, or system productization based on domestic processes.</li><li>· Ability to conduct independent research on focused topics, track frontier technologies, propose new ideas, and validate technical judgments through modeling, data, and experiments.</li><li>· Strong cost awareness and engineering judgment, able to make sound trade-offs among performance, power, cost, development cycle, and supply-chain availability.</li><li>· Familiarity with the key characteristics of large-model inference, including Attention, MoE, low-precision computation, KV cache, Prefill/Decode, and model parallelism, and the ability to analyze their demands on compute, memory, and communication resources.</li><li>· Interconnect direction: high-speed SerDes, die-to-die, PCIe, dedicated inter-card interconnect, or RDMA networks, with an in-depth understanding of how topology, bandwidth, latency, and communication efficiency impact system performance.</li><li>· In-depth architecture design capability and hands-on project experience in at least one of the following areas:</li></ol>

Senior Architect (GPU/NPU Frontier Technology & System Innovation)

- Possesses a Bachelor/ Master degree or above in Science, Engineering, Technology or STEM-related discipline. - Conducts in-depth researches on the technological innovations within the digitalized experience domain, focusing on the applications in the fields of rehabilitation, healthcare and educational technologies. - Analyzes data and trends in the field to stay updated on the latest advancements for further technology innovation and improvement opportunities. - Drive innovations by exploring new ideas, technologies, and methodologies that can positively impact digitalized experiences in rehabilitation, healthcare, and education. - Contributes to the development of new technologies or the adaptation of existing technologies for use in rehabilitation, healthcare, and educational settings. - Collaborates and works closely with interdisciplinary teams, including researchers, engineers, professionals and domain experts, to develop and implement technology-driven solutions. - Implements research projects with deliverables achieved and archived in the reports, research papers, and presentations to communicate and update the stakeholders in the academic and professional community. - Evaluate the effectiveness of existing technologies and propose enhancements or new solutions in the digitalized experience domain. - Ensure the quality and reliability of research data and outcomes through rigorous testing, validation, and adherence to best practices-

Researcher (Digitalization, Innovation and Technology)

FinTech Algorithm EngineerDeepstone Tech📍 Hong Kong SAR ｜ On-site ｜ Full-timeTags:Cryptography · Rust · C++ · Optimization · Machine LearningJob Vacancy DetailsFinTech Algorithm EngineerThe successful candidate will join the core algorithm team at Deepstone Tech and, under the guidance of senior engineers, help build the critical algorithms and systems that power our fintech products — spanning high-performance computing, optimization modeling, machine learning, and applied cryptography.Key Responsibilities<ul data-markdown-list="unordered" data-streamdown="unordered-list"><li data-streamdown="list-item">Participate in the design, development, and optimization of core financial algorithms, including pricing models, risk measurement, and portfolio optimization</li><li data-streamdown="list-item">Assist in building and maintaining machine learning models (market signals, anomaly detection, predictive modeling) and deploying them to production</li><li data-streamdown="list-item">Develop production-grade system components in Rust or C++, with opportunities to learn profiling and performance tuning</li><li data-streamdown="list-item">Take part in code reviews and technical discussions, working closely with senior engineers and researchers to grow into a well-rounded algorithm engineer</li><li data-streamdown="list-item">Track emerging developments in academia and industry and explore their potential application in our products</li></ul>RequirementsWe are seeking a high-potential candidate with the following profile:<ul data-markdown-list="unordered" data-streamdown="unordered-list"><li data-streamdown="list-item">Bachelor's degree or above in Computer Science, Mathematics, Applied Mathematics, Operations Research, Cryptography, Financial Engineering, or a related discipline</li><li data-streamdown="list-item">1–3 years of experience in algorithm development, software engineering, or a related field (outstanding fresh graduates are also welcome to apply)</li><li data-streamdown="list-item">Proficiency ineither Rust or C++— one of the two is sufficient</li><li data-streamdown="list-item">A solid foundation inat least oneof the following areas (no need to master all):<ul data-markdown-list="unordered" data-streamdown="unordered-list"><li data-streamdown="list-item">Cryptography— symmetric/asymmetric encryption, hash functions, digital signatures, or a strong interest in ZKP/MPC</li><li data-streamdown="list-item">Optimization— linear/quadratic programming, convex optimization, numerical methods, or hands-on experience with any solver</li><li data-streamdown="list-item">Machine Learning— end-to-end project experience, proficiency in PyTorch or TensorFlow</li></ul></li><li data-streamdown="list-item">Good written and verbal communication skills in both English and Chinese</li><li data-streamdown="list-item">Strong curiosity, a growth mindset, and the ability to deliver independently under senior guidance</li></ul>Office Location: Hong Kong Science Park, Shatin，19WRemuneration:A monthly salary of approximately HK$28,000 – HK$32,000, commensurate with qualifications and experience, plus annual bonus, medical insurance, and learning support.Application:Interested parties please send a full resume todeepstonetech@gmail.com. Applications will be processed on a rolling basis. Only shortlisted candidates will be notified.Data collected will be used for recruitment purpose only.

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